1. Field of the Invention
The present invention relates generally to silicon structures for performing the learning function in neural networks and like systems. More particularly, the present invention relates to a single transistor analog floating gate MOS memory device which incorporates a capability for simultaneous memory reading and writing as part of the normal MOSFET device operation and which is suitable for performing long-term learning in silicon integrated circuits.
2. The Prior Art
One impediment to the development of silicon learning networks is the difficulty in storing analog weight values on-chip. Prior efforts typically used capacitive storage with clocked refresh, B. Hochet, et al., "Implementation of a Learning Kohonen Neuron Based on a New Multilevel Storage Technique," IEEE J. Solid-State Circuits, Vol. 26, No. 3, 1991, pp. 262-267, or storage of a multi-bit digital equivalent word, P. Hollis, et al., "A Neural Network Learning Algorithm Tailored for VLSI Implementation," IEEE Tran. Neural Networks, Vol. 5, No. 5, 1994, pp. 784-791. Both of these approaches pay a large price in terms of cell size, resolution, complexity and power consumption.
To achieve a substantial improvement over current technology silicon learning systems a single transistor learning device with the following attributes would be very valuable:
1. Non-volatile analog storage; PA1 2. Bi-directional memory writing; PA1 3. Support for simultaneous memory reading and writing; PA1 4. On-chip read/write driver circuitry operating off of a single polarity voltage supply; PA1 5. Low power consumption; PA1 6. Compact size; and PA1 7. Compatibility with standard silicon MOS processing.
Prior art floating gate transistors, which use electrical charge stored on a floating polysilicon gate embedded in an insulator such as silicon dioxide, provide suitable non-volatile analog storage. The charge on such a floating gate is known to remain fixed for periods of many years. Although the advantages of using floating gate transistors as memory elements are well known, J. Lazzaro, et al., "Systems Technologies for Silicon Auditory Models," IEEE Micro, Vol. 14, No. 3, 1994, pp. 7-15, T. Allen, et al., U.S. Pat. No. 5,166,562, entitled: "Writable Analog Reference Voltage Storage Device," their application to silicon learning networks has been limited. The principal reason has been the lack of a suitable bi-directional mechanism for writing the analog memory. Since the gate of a floating gate transistor is completely embedded within an insulator, writing the memory involves moving charge carriers through this insulator. Two mechanisms are known which will move electrons through an insulator. These are tunneling and hot-electron injection. The inherent difficulty in performing these operations has been the primary impediment to implementation of floating gate transistors in silicon learning systems.
The difficulty in transporting electrons across the barrier presented by the silicon/oxide interface is depicted in FIG. 1A. Surmounting the barrier requires that an electron possess more than about 3.1 eV of energy. At room temperature the probability that semiconductor electrons will possess this energy is exceedingly small. Alternatively, an electron could tunnel through this barrier; however, at the voltages and oxide thicknesses used in conventional silicon MOS processing, the tunneling probability is also exceedingly small.
Fowler-Nordheim tunneling involves applying a voltage across the oxide, as shown in FIG. 1B, which enhances the probability of an electron tunneling through it. Tunneling current vs. oxide voltage for a 400.ANG., SiO.sub.2 gate oxide typical of a 2 .mu.m MOS process is shown in FIG. 1C. Bi-directional oxide currents are required to achieve the learning and unlearning functions necessary in a silicon learning cell. Although the tunneling process has no preferred direction, bi-directional tunneling requires either dual polarity high voltages, or a single polarity high voltage and a means for pulling the floating gate to this voltage when adding electrons, and pulling it near ground when removing them. Both approaches are unattractive. The dual polarity solution requires a negative voltage much lower than the substrate potential; the single polarity solution does not support simultaneous memory reading and writing.
Single polarity bi-directional tunneling is often used in writing digital EEPROMs. Since writing the memory involves pulling the floating gate either to the supply voltage or to ground, the EEPROM cell cannot be read during the write process. Excess charge is typically added to the floating gate to compensate for this lack of memory state feedback. Although excess charge is acceptable when writing a binary valued "digital" memory, where the exact quantity of charge is irrelevant once it exceeds the amount necessary to completely switch the device to one of its two binary states, uncertainty in the amount of charge applied to an analog memory cell results in significant memory error.
Hot-electron injection is a process whereby electrons near the surface of a semiconductor acquire more than about 3.1 eV of energy, typically by acceleration in an electric field, and then surmount the silicon/oxide barrier. Once in the silicon dioxide conduction band, an electric field applied across the oxide carries these electrons to the floating gate. There are a number of ways of accomplishing hot-electron injection.
One source for a high electric field is the collector-to-base depletion region of either a vertical or lateral BJT (bipolar junction transistor). An example of a lateral BJT used in a similar application is shown in U.S. Pat. No. 4,953,928 to Anderson et al. Although this device is suitable for analog learning applications, each learning cell requires both an injection BJT and a MOSFET, the former to effect hot-electron injection and the latter to read the stored charge. A reduction in the number of transistors per cell would be highly desirable.
Another source for a high electric field is in the channel region of a split-gate N-type MOSFET. Split-gate injectors, as shown and described in U.S. Pat. No. 4,622,656 to Kamiya, et al., contain two partially overlapping gate regions at very different voltages. The resulting surface potential drops abruptly at the interface between the two gates, creating a high electric field localized in this small region of the transistor channel. Unfortunately, since the control gate modulates the injection rate but does not receive the injected charge, the memory cannot be both written and read simultaneously. Such a device is acceptable for digital EEPROMs but is unsuitable for analog learning cell applications.
A third source for high electric field is the drain to source voltage dropped across the channel region of an above-threshold sub-micron N-type MOSFET. The disadvantage of this device is that in order achieve injection, both the drain and gate voltages must exceed approximately 2.5 volts which results in high channel current and consequent high power consumption.
A fourth source for high electric field is the drain to channel depletion region formed in an N-type MOSFET. In a conventional MOSFET, as depicted in FIG. 2A-2B, this field only exists when the drain-to-source voltage exceeds 2.5 volts and the transistor is operated at or near its subthreshold regime. Since subthreshold MOSFET gate voltages are typically less than one volt, electrons injected into the gate oxide encounter a large electric field directed towards the transistor drain, opposing their transport to the floating gate. The resulting charge transfer to the floating gate is negligibly small as can be seen in the FIG. 2B energy band diagram of the transistor of FIG. 2A.
Accordingly, there is a need for an improved silicon analog memory cell which can be written and erased, which can be written and read simultaneously, and which can be realized in a single device.